已经照这个设置配置ide:RISC-V IDE MRS使用笔记(三):提升浮点计算效率_riscv 浮点计算 不同的优化编译等级,精确度不一样_MounRiver_Studio的博客-CSDN博客
但是没说rtthread怎么配,我就在cpuport.h设置如下:
/* bytes of register width 浮点开启,还有ide设置也要开启 */
#define ARCH_RISCV_FPU
//#define ARCH_RISCV_FPU_D
但是还是编译不过:
G:/svn_new/zx-multifuncbrd/trunk/common/rtthread/libcpu/risc-v/common/context_gcc.S: Assembler messages:
G:/svn_new/zx-multifuncbrd/trunk/common/rtthread/libcpu/risc-v/common/context_gcc.S:47: Error: unrecognized opcode `fsd f0,0*8(sp)'
G:/svn_new/zx-multifuncbrd/trunk/common/rtthread/libcpu/risc-v/common/context_gcc.S:48: Error: unrecognized opcode `fsd f1,1*8(sp)'
G:/svn_new/zx-multifuncbrd/trunk/common/rtthread/libcpu/risc-v/common/context_gcc.S:49: Error: unrecognized opcode `fsd f2,2*8(sp)'
要怎么配呢?