假定，程序只有 一个 INT0 外部中断，下降沿中断，优先级高。（即不考虑程序的影响，单纯硬件上考虑）

当外部发生下降沿， 单片机保存 PC地址 然后跳转到 0003

请问，从下降沿发生，到从0003地址开始执行 代码，这个过程，总共会经历多少个系统时钟？

加强型51机器周期和时钟周期几乎一致，运行跳转中断，大概会经过两次跳转，可以转成汇编看下具体的代码查看用到的指令条数，具体的指令及其对应的周期数可以参考这个文档：

https://www.wch.cn/downloads/CH554EVT_ZIP.html

EVT->PUB->CH55X汇编指令.PDF

你好，指令周期我会看，我本来就是用汇编写的代码，所以不用转，你给我指令周期表，我不知道有什么用，从外部中断0 触发下降沿，到PC指针 指向0x0003这个过程，指令周期表上能查到？我所需要知道的，就是从外部给信号，到单片机PC指针跳转到 0x0003这个地址为止，需要多少时间？？

Latency should be at most the execution time of LCALL + 7

worst is 12 clocks

best is 6 clocks

@usbman

The Latency information is useful. Is there any source for that kind of info?

its hard to find realable sources for that these days. Maybe this helps:

Understanding Interrupt Latency in Modern 8051s — CAST Technical Article | ChipEstimate.com

some explanations:

1. before a interrupt is accepted the last cmd must terminate. On an old 12 clocker this can eat up to 48 cycles (MUL / DIV) ON E8051 its 6/7clocks 

2. executing the irq vector is like a LCALL 0x0003

3. at irq vector most of the time there ist LJMP ISR_Routine which adds another 6/7 cycles

4. if there is already another irq running with the same priority the runtime of that irq must be added too.

so in fact before the first cmt of the ISR_Routine is executed it takes 7 + 2 * 7 clocks at worse

or 1 + 2*6 at best. Also the priority reg must be reviewed when more than one IRQ source is enabled.

These calulations are just for a idle system using the exec times published from WCH.

Maybe one of the FAEs can put some extra light on that.

Thank you for your explanation. 

I tried to have the main code to flip an IO, and flip another IO at the beginning of Interrupt handler. The latency is about 14 clock. That is about 2 of the LJMP.